In order to achieve the layout freedom of a cell (also termed as a macro cell or a primitive cell) in a power supply interconnection structure of a semiconductor integrated circuit, the thickness and width of a power supply line, the number of power supply vias, the distance between power supply lines are determined in consideration of power supply to a high drive cell such as a buffer having a high driving capability and the like.
There has been known a power supply interconnection structure of a semiconductor for making it possible to layout a driver circuit having a high driving capability without increasing the chip area, in which a macrocell such as a clocked driver having large fan-out is disposed below a power supply line (refer to, for example, Patent specification 1).
Recently, an on-chip decoupling capacitor which uses a MOS gate capacitor in a semiconductor integrated circuit has been adopted as a decoupling capacitor provided between a power supply line and the ground line to reduce power supply noise. In association with an increase in operation frequency and an increase in power supply current of a semiconductor integrated circuit, the capacitance of the on-chip decoupling capacitor is increased, resulting in an increase in area which is required for a capacitor on a chip. In order to overcome such a problem, a structure decoupling capacitor which achieves an improvement in area efficiency has been proposed (refer to, for example, Patent specification 2). This structure of decoupling capacitor has an ESD (electrostatic discharge) immunity without requiring the step for forming a resistor for preventing ESD. As will be described hereafter, a capacitor cell which is used in embodiments of the present invention uses the decoupling capacitor which is described in the above-mentioned Patent specification 2 as a capacitor element structure.
A structure which reduces the number of steps required for enhancing the power supply line and does not cause an increase in chip size in a power supply device for a semiconductor integrated circuit has been known (refer to, for example, Patent specification 3). This power supply device for a semiconductor integrated circuit comprises an internal integrated circuit area which operates at a reference supplied voltage; a voltage drop analyzing means which can detect a drop of voltage which is caused by the internal integrated circuit area; a step up converter circuit which can apply a voltage higher than said reference supplied voltage to the internal integrated circuit area; and feeding back means for feeding back to the step up converter circuit the voltage drop caused by the internal integrated circuit area, which is detected by the voltage drop analyzing means, so that the voltage drop caused by the internal integrated circuit falls within a designed tolerance range. Cited Patent Specification 3 describes that a problem of the voltage drop can be overcome by applying stepped up a reference supplied voltage to the internal integrated circuit, if the analyzing means shows that the voltage drop after the interconnection is disposed is lower than the designed tolerance range (margin), that the number of steps required for enhancing the power supply line can be reduced and that an increase in chip size is not caused. However, the structure of the power supply enhancing circuit of the Patent specification 3 includes a voltage drop detecting circuit and feeding back circuit for supplied voltage and the like, which brings an increase in circuit scale.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-6-236923 (Page, 5, FIG. 4)
[Patent Document 2]
Japanese Patent Kokai Publication No. JP-P2003-86699A (FIG. 2)
[Patent Document 3]
Japanese Patent Kokai Publication No. JP-P2002-313929A (Page 4, FIG. 1)